VHDL Entity

Each VHDL entity declaration is transformed into a C++ class. All port signals, generic parameters and other named entities^7.1 declared within the declarative region of the entity are represented by corresponding class variables.

The constructor elaborates the declaration part of the entity. Moreover, it initialises all objects which represent port signals and generic parameters (formals of the entity declaration) and binds them to the actual signal respectively parameter objects (actuals) of the enclosing entity-architecture.