C++ Naming Conventions

During transformation of VHDL to C++ various VHDL named entities^3.1 like VHDL entity's, architectures, variables ...are translated into corresponding C++ classes, functions or objects. To uniquely distinguish the classes from each other, the following generation rules to create C++ names from VHDL named entity's are used:

1.

All letters of a entity name are converted into small characters. Additionally, the length of the entity string is prepended in decimal format. Further, a capital letter (class identifier) describing the class of the entity is prepended. The class of the entity corresponds with the following identifier:

VHDL class	ident
library	L
package	Q
entity	E
architecture	A
block	B
label	L
process	P
type	T
driver	D

VHDL class	ident
procedure	X
function	F
variable	V
constant	C
signal	S
generic	G
configuration	K
type information	I
signal reader	R

2.

If a created name consists of several VHDL entity names they are converted separately and appended afterwards. A character '_' is used to connect the converted names.

Example: A VHDL function named ``Vhdl_func'' which is declared within a architecture ``behave'' of an entity ``test'' belonging to library ``lib'' is named L3lib_E3test_A6behave_F9vhdl_func.