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Compiling a VHDL description into a simulation program is done in four
phases:
- 1.
- Scanner/parser phase
- 2.
- Code generation phase
- 3.
- Intermediate language compilation phase
- 4.
- Linking phase.
During the first phase the VHDL source is scanned and parsed. The
scanner/parser checks the source syntactically and semantically and
builds an abstract syntax tree which includes all information
necessary to enter the code generation phase. During code generation
the nodes of the tree are transformed into corresponding C++
(intermediate language) constructs which are compiled during the next
phase (intermediate language compilation stage) into object
code. Finally, all object modules of the VHDL model are linked
together with the simulation kernel and a interface module to
form a simulation program. The interface module is connected with
the SCS (simulation control centre) via network. The SCS reads in user
commands (i.e. start/stop simulation, show signal values, ...) and
send them to the user interface module which translates them into
corresponding kernel actions. In turn, all (stdout) output generated
by the simulator is send to the SCS.
The code generator creates
- the structure elaboration code,
- the code to emulate the behaviour of the VHDL processes,
functions, procedures and finally
- the type handling code
from the syntax tree. The job of the structure elaboration code is to
instantiate all signal and process instances of the model and bind
them to the simulation kernel. After structure elaboration has
finished the VHDL model consists of a set of processes and
signals. Controlled by the simulation kernel processes are
executed and values are assigned on signals.
The type handling code implements functionality used to perform basic
operations (assignment, compare, ...) on objects (signals, variables
...) of user defined types. Additionally, it provides some special
handling functions to the simulation kernel. This functions are
required because user defined types are unknown to the kernel at
kernel compile time while code generated by the code generator can
handle user defined types directly.
Next: Conventions
Up: The FreeHDL Compiler/Simulator System
Previous: Document History
1998-11-17