Wait Statement

If a process hits a wait statements its execution is suspended. The wait statements informs the simulation kernel under which conditions the process should resume. In detail a wait statement consists of three components.

• Sensitivity list:

  The sensitivity list lists the signal(s) the process will be sensitive on. If at least one of this signal(s) changes its value the process will resume. The sensitivity list can be defined explicitly by the VHDL source code or may be determined from a wait condition expression by the compiler.

• Wait condition:

  A wait condition defines an boolean expression which will be evaluated if a signal on the sensitivity lists changes. Only if the condition evaluates to true the process will resume. If no wait condition has been specified in the source code it is implicitly set to true.

• Timeout clause:

  The suspended process will resume, at the latest, immediately after the timeout interval specified in the time out clause has expired. If no timeout interval is specified in the VHDL source, the interval is set to infinity. If no sensitivity list and no wait condition are specified the process will wait for the amount of time given by the timeout interval.

All three parts of a wait statement are optional, however the sensitivity list is determined by the compiler if it is not specified in the VHDL source directly. Note, if the sensitivity list is empty and there is no timeout interval defined, then the process will be terminated.