Concurrent Statements

In VHDL the behaviour of a component can be defined in several ways:

• Processes may be used to describe the behaviour algorithmically. While all processes included in a design virtually operate in parallel, the statements within a process are executed sequentially similar to common programming languages like C, C++, or Pascal. However, there are special statements defined in VHDL which allow to suspend/resume execution of a process. Actually, this statements (or a similar construct) must be used in order to increase simulation time during simulation.

• Concurrent signal assignment statements calculate new values for signals from an expression. The expression is reevaluated and reassigned whenever a signal within the expression changes its value. Actually, concurrent signal assignments are represented by specialised processes.

• Component instantiation statements are used to construct a component from a set of smaller components. These statements are executed at elaboration time only. Their single effect is to instantiate other components and connect them with the current component.

Processes, concurrent signal assignments, and component instantiations may be mixed arbitrarily in order to describe the structure respectively behaviour of a new component.

Note, after elaboration the entire VHDL model consists solely of a set of processes and signals. The processes communicate with each other by reading/writing on these signals respectively shared variables.