VHDL subprograms defined within an architecture declaration region are mapped to corresponding member functions. Additionally, each architecture class contains a constructor and destructor.
Method | Description |
'ArchitectureClass' (
name_stack iname, map_list *mlist) |
Elaborates the declaration part of the architecture. The parameter ``iname'' is the instance name of the current component and ``mlist'' pointer to a list containing the mapping information for the port signals and generic parameters of the corresponding entity. |
~ 'ArchitectureClass' () | The destructor cleans up memory if a component is removed. |
Example:
ARCHITECTURE behave OF myentity IS SIGNAL localsig : INTEGER; BEGIN p: PROCESS (...) BEGIN ... END PROCESS; fcomp: FOR i IN 0 TO genpar GENERATE ccc: ENTITY foo(fooarch) PORT MAP (...); END GENERATE; END behave;is transformed to
class L7testlib_E8myentity_A6behave : L7testlib_E8myentity { public: signal<L3std_Q8standard_T7integer> *S8localsig; L7testlib_E8myentity_A6behave(); ~L7testlib_E8myentity_A6behave(); }; L7testlib_E8myentity_A6behave::L7testlib_E8myentity_A6behave( string iname, map_list *mlist) : L7testlib_E8myentity(iname, mlist) { // create process named ``p'' and link it with the kernel kernel.add_process(new L7testlib_E8myentity_A6behave(this, iname.get_name()), iname.push(":p")); iname.set(":fcomp"); // set ``:fcomp'' as the current instance name iname.push(""); // push a dummy entry on the stack // execute the generate loop for (int V1i=0; V1i < G6genpar; V1i++) { iname.set(V1i); // replace top entry with ``(?)'' map_list ml; // create map list and add mapping information ... // to the list iname.push(":ccc"); // add ``:ccc'' to current instance name // call constructor of component via a kernel call kernel.elaborate_component("","foo","fooarch",iname,&ml); iname.pop(); // remove ``:ccc'' from name stack } iname.pop(); // remove ``(?)'' from current instance name iname.pop(); // remove ``:fcomp'' from current instance name };